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s3c72g9/p72g9 product overview 1 - 1 1 product overview overview the s3c72g9 single-chip cmos microcontroller has been designed for high performance using samsung's newest 4 - bit cpu core, sam47 (samsung arrangeable microcontrollers). with an up-to- 896 -dot lcd direct drive capability, and flexible 8-bit timer/counter s , the s3c72g9 offers an excellent design solution for a high-end lcd game . up to 12 pins of the 100 -pin qfp package can be dedicated to i/o. seven vectored interrupts provide fast response to internal and external events. in addi tion, the s3c72g9 's advanced cmos technology pro vides for low power consumption. otp the s3c72g9 microcontroller is also available in otp (one time programmable) version, S3P72G9. S3P72G9 microcontroller has an on-chip 32 k-byte one-time-programmable eprom instead of masked rom. the S3P72G9 is comparable to s3c72g9, both in function and in pin configuration.
product overview s3c72g9/p72g9 1 - 2 features memory ? 768 4-bit ram (excluding lcd display ram) ? 32 , 768 8-bit rom 12 i/o pins ? i/o: 12 pins lcd controller/driver ? 56 segments and 16 common terminals (8, 12 and 16 common selectable ) ? capacitor bias for lcd output. ? voltage booster and regulator ? all dot s can be switched on/off 8-bit basic timer ? 4 interval timer functions ? watch-dog timer one 16-bit timer/counter 1 ? programmable 16 -bit timer ? arbitrary clock output (tclo1) ? inverted clock output ( tclo 1) ? configurable two 8-bit timer/counters watch timer ? time interval generation: 0.5 s, 3.9 ms at 32768 hz ? four frequency outputs to buz pin and buz pin ? clock source generation for lcd battery level detector ? programmable low voltage detector ? one criteria voltage (2.4 v) interrupts ? three i nternal vectored interrupt ? four external vectored interrupts ? two quasi-interrupts memory-mapped i/o structure ? data memory bank 15 power-down modes ? idle mode (only cpu clock stops) ? stop mode (main system oscillation stops) ? subsystem clock stop mode oscillation sources ? crystal, ceramic, or rc for main system clock ? crystal oscillator for subsystem clock ? main system clock frequency: 0.4- 4.19 mhz ? subsystem clock frequency: 32.768 khz ? cpu clock divider circuit (by 4, 8, or 64) instruction execution times ? 0.95, 1.91, 15.3 s at 4.19 mhz (main) ? 122 s at 32.768 khz (subsystem) operating temperature ? ? 40 c to 85 c operating voltage range ? 2. 2 v to 3 . 4 v (0.4 mhz to 4.19 mhz) package type ? 100-pin qfp or pellet
s3c72g9/p72g9 product overview 1 - 3 block diagram instruction register arithmetic and logic unit instruction decoder internal interrupts interrupt control block clock 32-kbyte program memory x out x tout x in x tin program counter program status word stack pointer reset 768 x 4-bit data memory watch timer basic (watchdog) timer voltage regulator/ booster lcd driver/ controller battery level detector test 2 ca cb seg0-seg55 vlc1-vlc5 16-bit timer counter 1 i/o port 1 i/o port 0 i/o port 2 p1.3/int4 p1.2/int2 p1.1/int1 p1.0/int0 p0.3/buz/k3 p0.2/ buz /k2 p0.1/ tclo1 /k1 p0.0/tclo1/k0 p2.0/clo p2.1/tcl1 p2.2 p2.3 8-bit timer counter 1a 8-bit timer counter 1b com0-com15 figure 1-1 . s3c72g9 simplified block diagram
product overview s3c72g9/p72g9 1 - 4 pin assignments seg17 seg16 seg15 seg14 seg13 seg12 seg11 seg10 seg9 seg8 seg7 seg6 seg5 seg4 seg3 seg2 seg1 seg0 vlc1 vlc2 seg48 seg49 seg50 seg51 seg52 seg53 seg54 seg55 com0 com1 com2 com3 com4 com5 com6 com7 com8 com9 com10 com11 seg18 seg19 seg21 seg22 seg22 seg23 seg24 seg25 seg26 seg27 seg28 seg29 seg30 seg31 seg32 seg33 seg34 seg35 seg36 seg37 seg38 seg39 seg40 seg41 seg42 seg43 seg44 seg45 seg46 seg47 vlc3 vlc4 vlc5 ca cb test2 p1.3/int4 p1.2/int2 p1.1/int1 p1.0/int0 buz/p0.3/k3 buz /p0.2/k2 tclo1 /p0.1/k1 tclo1/p0.0/k0 v dd v ss x out x in test1 x t in xt out reset clo/p2.0 tcl1/p2.1 p2.2 p2.3 com15 com14 com13 com12 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ks57c21632 100-qfp 1420 c figure 1-2 . s3c72g9 10 0-qfp pin assignment diagram
s3c72g9/p72g9 product overview 1 - 5 pin descriptions table 1- 1. s3c72g9 pin descriptions pin name pin type description number share pin p0.0 p0.1 p0.2 p0.3 i/o 4-bit i/o port. 1-bit and 4-bit read/write and test are possible. individual pins are software configurable as input or output. individual pins are software configurable as open- drain or push-pull output. individual pull-up resistors are software assignable; pull-up resistors are automatically disabled for output pins. 14 13 12 11 tclo1 /k0 tclo 1/k1 buz / k2 buz/k3 p1.0 p1.1 p1.2 p1.3 i /o same as port 0 10 9 8 7 int0 int1 int2 int4 p2.0 p2.1 p2.2 p2.3 i /o same as port 0 23 24 25 26 clo tcl1 int0, int1 i/o external interrupts. the triggering edge for int0 and int1 is selectable. 10, 9 p1.0, p1.1 int2 i/o quasi-interrupt with detection of rising or falling edges. 8 p1.2 int4 i/o external interrupt with detection of rising and falling edges. 7 p1.3 buz i/o 2 khz, 4 khz, 8 khz or 16 khz frequency output for buzzer signal. 11 p0.3/k3 buz i/o inverted buz signal 12 p0.2/k2 clo i/o clock output 23 p2.0 tcl1 i/o external clock input for timer/counter 1 24 p2.1 tclo 1 i/o timer/counter 1 inverted clock output 13 p0.1/k1 tclo1 i/o timer/counter 1 clock output 14 p0.0/k0 com0?com15 o lcd common signal output 42-27 ? seg0?seg55 o lcd segment signal output 98-43 ?
product overview s3c72g9/p72g9 1 - 6 table 1- 1. s3c72g9 pin descriptions (continued) pin name pin type description number share pin k0 ? k3 i/o external interrupt (triggering edge is selectable) 14?11 p0.0 ? p0.3 v dd ? main power supply 15 ? v ss ? ground 16 ? reset i reset signal 22 ? ca, cb ? capacitor terminal for voltage boosting 4, 5 ? vcl1?vcl2 vcl3?vcl5 ? lcd power supply 99?100 1?3 ? test2 i test input (must be connected v ss ) 6 ? x in , x out ? crystal, ceramic or rc o scillator pins for system clock 18, 17 ? xt in , xt out ? crystal oscill ator pins for subsystem clock 20, 21 ? test 1 i test input (must be connected to v ss ) (2) 19 ? note s 1. pull-up resistors for all i/o ports are automatically disabled if they are configured to output mode. 2. refer to chapter 16 for otp version. table 1-2 . overview of s3c72g9 pin d ata pin name share pins i/o type reset value circuit type p0.0?p0.3 tclo1/k0, tclo 1/k1 buz /k2, buz/k3 i/o input e-2 p1.0?p1.3 int0, int1, int2, int4 i/o input e-2 p2.0?p2.1 clo, tcl1 i/o input e-2 p2.2?p2.3 ? i/o input e-2 com0?com15 ? o low h-6 seg0?seg55 ? o low h-6 v dd ? ? ? ? v ss ? ? ? ? reset ? i ? b ca ? ? ? ? cb ? ? ? ? vlc1?vlc5 ? ? ? ? x in , x out ? ? ? ? xt in , xt out ? ? ? ? test 1, 2 ? i ? ?
s3c72g9/p72g9 product overview 1 - 7 pin circuit diagrams p-channel n-channel in v dd figure 1-3. pin circuit type a in pull-up resistor v dd schmitt trigger figure 1-4 . pin circuit type b pne output disable data v dd resistor enable v dd i/o pull-up resistor schmitt trigger figure 1-5. pin circuit type e-2 out seg/com data v lc2 v lc3 /v lc4 v lc1 v lc5 v lc3 /v lc4 v ss figure 1-6 . pin circuit type h-6
s3c72g9/p72g9 electrical data 14- 1 14 electrical data overview in this section, information on s3c72g9 electrical characteristics is presented as tables and graphics. the information is arranged in the following order: standard electrical characteristics ? a bsolute maximum ratings ? d.c. electrical characteristics ? main system clock oscillator characteristics ? subsystem clock oscillator characteristics ? i/o capacitance ? battery level detector characteristics ? voltage booster characteristics ? a.c. electrical characteristics ? operating voltage range stop mode characteristics and timing waveforms ? ram data retention supply voltage in stop mode ? stop mode release timing when initiated by reset ? stop mode release timing when initiated by an interrupt requ est miscellaneous timing waveforms ? a.c timing measurement point ? clock timing measurement at x in ? clock timing measurement at xt in ? input timing for reset signal ? input timing for external interrupts and quasi-interrupts
electrical data s3c72g9/p72g9 14- 2 table 14- 1. absolute maximum ratings (t a = 25 c) parameter symbol conditions rating units supply voltage v dd ? ? 0.3 to + 4.5 v input voltage v i ports 0 ?2 ? 0.3 to v dd + 0.3 v output voltage v o ? ? 0.3 to v dd + 0.3 v output current high i oh one i/o p in active ? 15 ma all i/o p ins active ? 30 output current low i ol one i/o p in active + 30 (peak value) ma + 15 (note) total for p ins 0, 1 + 100 (peak value) + 60 (note) operating temperature t a ? ? 40 to + 85 c storage temperature t stg ? ? 65 to + 150 c note: the values for output current low ( i ol ) are calculated as peak value duty . table 14- 2. d.c. electrical characteristics (t a = ? 40 c to + 85 c, v dd = 2. 2 v to 3.4 v) parameter symbol conditions min typ max units input high voltage v ih1 ports 0, 1 , 2 , and reset 0. 8 v dd ? v dd v v ih2 x in , x out , and xt in v dd ? 0.1 v dd input low voltage v il1 ports 0, 1, 2, and reset ? ? 0. 2 v dd v v il2 x in , x out , and xt in 0. 1 output high voltage v oh v dd = 2. 2 v to 3.4 v i oh = ? 1 ma ports 0, 1, 2 v dd ? 1.0 ? ? v output low voltage v ol v dd = 2. 2 v to 3.4 v i ol = 5 ma ports 0, 1, 2 ? ? 1.0 v
s3c72g9/p72g9 electrical data 14- 3 table 14-2. d.c. electrical characteristics (continued) (t a = ? 40 c to + 85 c, v dd = 2.2 v to 3.4 v) parameter symbol conditions min typ max units input high leakage current i lih1 v i = v dd all input pins except those specified below for i lih2 ? ? 3 a i lih2 v i = v dd reset, x in , x out, xt in and xt out 20 input low leakage current i lil1 v i = 0 v all input pins except reset, x in, x out, xt in and xt out ? ? ? 3 a i lil2 v i = 0 v x in, x out, xt in and xt out ? 20 output high leakage current i loh v o = v dd all output pins ? ? 3 a output low leakage current i lol v o = 0 v all output pins ? ? ? 3 a pull- u p resistor r l 1 v i = 0 v; v dd = 3 v , po rt s 0 ?2 50 100 200 k w r l 2 v i = 0 v; v dd = 3 v , reset 200 450 800 |v lcd ?comi| voltage drop ( i = 0?15) v dc v lc d = 5.0 v ? 15 a per common pin ? ? 120 mv |v lcd ?segx| voltage drop ( i = 0?55) v ds v lc d = 5.0 v ? 15 a per common pin ? ? 120
electrical data s3c72g9/p72g9 14- 4 table 14- 2. d.c. electrical characteristics (concluded) (t a = ? 40 c to + 85 c, v dd = 2. 2 v to 3.4 v) parameter symbol conditions min typ max units supply current (1) i dd1 v dd = 3 v 10% crystal o scillator c1 = c2 = 22 pf 4.19 mhz (pcon = 3h) ? 1.2 3 ma i dd 2 idle mode; v dd = 3 v 1 0% crystal oscillator c1 = c2 = 22 pf 4.19 mhz (pcon = 3h) ? 0.4 1 ma i dd 3 (2) v dd = 3 v 10% 32 khz crystal oscillator ? 15 30 m a i dd 4 (2) idle mode; v dd = 3 v 1 0% 32 khz crystal oscillator (lcd off) ? 6 15 m a i dd 5 stop mode; v dd = 3 v 10% scmod = 0000b, xt in = 0 v ? 0.5 3 m a stop mode; v dd = 3 v 10% scmod = 0000b 0.2 2 notes: 1 . data incl udes power consumption for subsystem clock oscillation. 2 . when the system clock control register, scmod, is set to 1001b, main system clock oscillation stops and the subsystem clock is used. 3. current in the following circuits are not included; on-chip pull-up resistors, internal lcd voltage booster circuit, and output port drive currents.
s3c72g9/p72g9 electrical data 14- 5 table 14- 3. main system clock oscillator characteristics (t a = ? 40 c to + 85 c, v dd = 2. 2 v to 3.4 v) oscillator clock configuration parameter test condition min typ max units ceramic oscillator x in c1 c2 x out oscillation frequency (1) ? 0.4 ? 4.19 mhz stabilization time (2) stabilization occurs when v dd is equal to the m inimum oscillator voltage range; v dd = 3 v ? ? 4 ms crystal oscillator x in c1 c2 x out oscillation frequency (1) ? 0.4 ? 4.19 mhz stabilization time (2) v dd = 3 v ? ? 10 ms external clock x in x out x in input frequency (1) ? 0.4 ? 4.19 mhz x in input high and low level width (t xh, t xl ) ? 83.3 ? 1250 ns rc oscillator x in x out r frequency v dd = 3 v 0.4 ? 2 mhz notes: 1. oscillation frequency and x in input frequency data are for oscillator characteristics only. 2. stabilization time is the interval required for oscilla tor stabilization after a power-on occurs, or when stop mode is terminated.
electrical data s3c72g9/p72g9 14- 6 table 14-4 . recommended oscillator constants (t a = ? 40 c + 85 c, v dd = 2.2 v to 3.4 v ) manufacturer series number (1) frequency range load cap (pf) oscillator voltage range (v) remarks c1 c2 min max tdk fcr ? e ? m5 3.58 mhz?6.0 mhz 33 33 2.2 3.4 leaded type fcr ? e ? mc5 3.58 mhz?6.0 mhz (2) (2) 2.2 3.4 on-chip c leaded type ccr ? e ? mc3 3.58 mhz?6.0 mhz (3) (3) 2.2 3.4 on-chip c smd type note s: 1. please specify normal oscillator frequency. 2. on-chip c: 30pf built in. 3. on-chip c: 38pf built in. table 14-5. subsystem clock oscillator characteristics (t a = ? 40 c to + 85 c, v dd = 2. 2 v to 3.4 v) oscillator clock configuration parameter test condition min typ max units crystal oscillator xt in c1 c2 xt out oscillation frequency (1) ? 32 32.768 35 khz stabilization time (2) v dd = 3.0 v ? 1.0 3 s external clock xt in xt out xt in input frequency (1) ? 32 ? 100 khz xt in input high and low level width (t xtl, t xth ) ? 5 ? 15 s notes: 1. oscillation frequency and xt in input frequency data are for oscillator characteristics only. 2. stabilization time is the interval required for oscillating stabilization after a power-on occurs.
s3c72g9/p72g9 electrical data 14- 7 table 14-6 . input/output capacitance (t a = 25 c, v dd = 0 v ) parameter symbol condition min typ max units input capacitance c in f = 1 mhz; unmeasured pins are returned to v ss ? ? 15 pf output capacitance c out ? ? 15 pf i/o capacitance c io ? ? 15 pf table 14-7 . battery level detector characteristics (t a = ? 40 c to + 85 c, v dd = 2.2 v to 3.4 v ) parameter symbol condition min typ max units bld voltage vb0 blc = 0 (when bref = #05h) 2.2 2.4 2.6 v bld circuit response time tb fw = 32.768 khz ? ? 1 ms bld operating current ibl ? ? ? 10 m a
electrical data s3c72g9/p72g9 14- 8 table 14-8 . voltage booster characteristics (t a = ? 40 c to + 85 c, v dd = 2. 2 v to 3.4 v , c1 = c2 = c3 = c4 = 0.1 m f, ca/cb = 0.1 m f ) parameter symbol conditions min typ max units liquid crystal drive voltage (1) v lc5 connect a 1 m w load resistance between v ss and v lc5 (2) (no panel load) lcr = 0 typ 0.9 0.85 typ 1.1 v lcr = 1 0.90 lcr = 2 0.95 lcr = 3 1.00 lcr = 4 1.05 lcr = 5 1.10 lcr = 6 1.15 lcr = 7 1.20 v lc4/3 connect a 1 m w load resistance between v ss and v lc4/3 (2) (no panel load) 2 v lc5 0.9 ? 2 v lc5 1.1 v lc2 connect a 1 m w load resistance between v ss and v lc2 (2) (no panel load) 3 v lc5 0.9 ? 3 v lc5 1.1 v lc1 connect a 1 m w load resistance between v ss and v lc1 (2) (no panel load) 4 v lc5 0.9 ? 4 v lc5 1.1 voltage regulator & booster consumed current ivb v dd = 3 v lcr = 7 display on (lcon = 3h) ? 5.0 10 m a notes: 1. the operating voltage of booster ranges from 2.4 v to 3.4 v. 2. the 1 m w load resistance is connected only to selected symbol (vlc1?vlc5) conditions to measure the properties of the circuit. table 14-9 . a.c. electrical characteristics (t a = ? 40 c to + 85 c, v dd = 2. 2 v to 3.4 v) parameter symbol conditions min typ max units instruction cycle time ( note ) t cy v dd = 2.2 v to 3.4 v 0.95 ? 64 s with subsystem clock (fxt) 114 122 125 interrupt input high, low width f inth, f intl int0?int2, int4 k0?k3, tlc1 10 ? ? m s reset input low wi dth t rsl input 10 ? ? m s note: unless otherwise specified, instruction cycle time condition values assume a m ain system clock ( fx ) source.
s3c72g9/p72g9 electrical data 14- 9 1.05 mhz cpu clock 15.6 khz main oscillator frequency (divided by 4) 4.2 mhz 1 2 3 4 5 6 7 3.4 2.2 supply voltage (v) cpu clock = 1/n x oscillator frequency (n = 4, 8 or 64) figure 14- 1. standard operating voltage range table 14-10 . ram data retention supply voltage in stop mode (t a = ? 40 c to + 85 c) parameter symbol conditions min typ max unit data retention supply voltage v dddr ? 2.2 ? 3.4 v data retention supply current i dddr v dddr = 2. 2 v ? 0.1 10 a release signal set time t srel ? 0 ? ? s oscillator stabilization wait time (1) t wait released by reset ? 2 17 /fx ? ms released by interrupt ? (2) ? notes : 1. during oscillator stabilization wait time, all cpu operations must be stopped to avoid instability during oscillator start-up. 2. use the basic timer mode register (bmod) interval timer to delay execution of cpu instructions during the wait time.
electrical data s3c72g9/p72g9 14- 10 timing waveforms execution of stop instrction internal reset operation ~ ~ v dddr ~ ~ stop mode idle mode normal mode data retention mode t srel t wait reset v dd figure 14- 2. stop mode release timing when initiated b y reset reset execution of stop instrction v dddr ~ ~ data retention mode v dd normal mode ~ ~ stop mode idle mode t srel t wait power-down mode terminating signal (interrupt request) figure 14- 3. stop mode release timing when initiated b y interrupt request
s3c72g9/p72g9 electrical data 14- 11 0.8 v dd 0.2 v dd 0.8 v dd 0.2 v dd measurement points figure 14- 4. a.c. timing measurement points (except for x in and xt in ) x in t xh t xl 1/fx v dd - 0.1 v 0.1 v figure 14- 5. clock timing measurement at x in x t in t xth t xtl 1/fxt v dd - 0.1 v 0.1 v figure 14- 6. clock timing measurement at x t in
electrical data s3c72g9/p72g9 14- 12 reset t rsl 0.2 v dd figure 14-7 . input timing for reset reset signal int0, 1, 2, 4, k0 to k3 tcl1 t inth t intl 0.8 v dd 0.2 v dd figure 14-8 . input timing for external interrupts
s3c72g9/p72g9 mechanical data 1 5- 1 15 mechanical data overview this section contains the following information about the device package: ? package dimensions in millimeters
mechanical data s3c72g9/p72g9 1 5- 2 100-qfp-1420c #100 20.00 23.90 14.00 17.90 0.15 + 0.10 - 0.05 0-8 0.10 max #1 0.65 note : dimensions are in millimeters. (0.58) 0.15 max 0.80 0.05 min 2.65 3.00 max 0.80 0.30 + 0.10 - 0.05 figure 15-1. 100-qfp-1420c package dimensions
s3c72g9/p72g9 S3P72G9 otp 16- 1 16 S3P72G9 otp overview the S3P72G9 single-chip cmos microcontroller is the otp (one time programmable) version of the s3c72g9 microcontroller. it has an on-chip otp rom instead of masked rom. the eprom is accessed by serial data format. the S3P72G9 is fully compatible with the s3c72g9, both in function and in pin configuration. because of its simple programming requirements, the S3P72G9 is ideal for use as an evaluation chip for the s3c72g9.
S3P72G9 otp s3c72g9/p72g9 16- 2 seg17 seg16 seg15 seg14 seg13 seg12 seg11 seg10 seg9 seg8 seg7 seg6 seg5 seg4 seg3 seg2 seg1 seg0 vlc1 vlc2 seg48 seg49 seg50 seg51 seg52 seg53 seg54 seg55 com0 com1 com2 com3 com4 com5 com6 com7 com8 com9 com10 com11 seg18 seg19 seg21 seg22 seg22 seg23 seg24 seg25 seg26 seg27 seg28 seg29 seg30 seg31 seg32 seg33 seg34 seg35 seg36 seg37 seg38 seg39 seg40 seg41 seg42 seg43 seg44 seg45 seg46 seg47 vlc3 vlc4 vlc5 ca cb test2 p1.3/int4 p1.2/int2 p1.1/int1 p1.0/int0 buz/p0.3/k3 buz /p0.2/k2 sdat / tclo1 /p0.1/k1 sclk /tclo1/p0.0/k0 v dd /v dd v ss /v ss x out x in v pp /test1 x t in xt out reset /reset clo/p2.0 tcl1/p2.1 p2.2 p2.3 com15 com14 com13 com12 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 S3P72G9 100-qfp 1420 c figure 16-1. S3P72G9 pin assignments (100-qfp package)
s3c72g9/p72g9 S3P72G9 otp 16- 3 table 16-1. descriptions of pins used to read/write the eprom main chip during programming pin name pin name pin no. i/o function p0.1 sdat 13 i/o serial data pin. output port when reading and input port when writing. can be assigned as a input/push- pull output port. p0.0 sclk 14 i/o serial clock pin. input only pin. test v pp (test1) 19 i power supply pin for eprom cell writing (indicates that otp enters into the writing mode). when 12.5 v is applied, otp is in writing mode and when 5 v is applied, otp is in reading mode. (option) reset reset 22 i chip initialization v dd /v ss v dd /v ss 15/16 i logic power supply pin. v dd should be tied to +5 v during programming. table 16-2. comparison of S3P72G9 and s3c72g9 features characteristic S3P72G9 s3c72g9 program memory 32 kbyte eprom 32 kbyte mask rom operating voltage (v dd ) 2.2 v to 3.4 v 2.2 v to 3.4 v otp programming mode v dd = 5 v, v pp (test1) = 12.5 v ? pin configuration 100 qfp 100 qfp eprom programmability user program 1 time programmed at the factory operating mode characteristics when 12.5 v is supplied to the v pp (test1) pin of the S3P72G9, the eprom programming mode is entered. the operating mode (read, write, or read protection) is selected according to the input signals to the pins listed in table 16-3 below. table 16-3. operating mode selection criteria v dd v pp (test1) reg/mem address (a15?a0) r/w mode 5 v 5 v 0 0000h 1 eprom read 12.5 v 0 0000h 0 eprom program 12.5 v 0 0000h 1 eprom verify 12.5 v 1 0e3fh 0 eprom read protection note : "0" means low level; "1" means high level.
S3P72G9 otp s3c72g9/p72g9 16- 4 table 16-4 . d.c. electrical characteristics (t a = ? 40 c to + 85 c, v dd = 2. 2 v to 3.4 v) parameter symbol conditions min typ max units supply current (1) i dd1 v dd = 3 v 10% 4.19 mhz (pcon = 3h) crystal o scillator c1 = c2 = 22 pf ? 1.2 3.0 ma i dd2 idle mode; v dd = 3 v 10% 4.19 mhz (pcon = 3h) crystal oscillator c1 = c2 = 22 pf 0.4 1.0 i dd3 ( 2 ) v dd = 3 v 10% 32 khz crystal oscillator ? 1 5 30 a i dd4 ( 2 ) idle mode; v dd = 3 v 10% 32 khz crystal oscillator 6 1.5 i dd5 stop mode; v dd = 3 v 10% scmod = 0000b, xt in = 0 v 0.5 3 stop mode; v dd = 3 v 10% scmod = 0100b 0.2 2 notes: 1. data includes power consumption for subsystem clock oscillation. 2. when the system clock control register, scmod, is set to 1001b, main system clock oscillation stops and the subsystem clock is used. 3. current in the following circuits are not included; on-chip pull-up resistors, voltage boosting capacitors, and output port drive currents.
s3c72g9/p72g9 S3P72G9 otp 16- 5 1.05 mhz cpu clock 15.6 khz main oscillator frequency (divided by 4) 4.2 mhz 1 2 3 4 5 6 7 3.4 2.2 supply voltage (v) cpu clock = 1/n x oscillator frequency (n = 4, 8 or 64) figure 16-2 . standard operating voltage range

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